Memory circuits with a number of access ports have become very popular and widely used in data communications and processing systems. One of the challenges associated with multi-port memories is how to resolve the situation where two ports attempt to access the same memory location at the same time. This situation can result in corruption of the stored data or corruption of the read-out data. A number of arbitration schemes have been proposed. One of the problems with prior art solutions is that they were developed to target two port memories. One arbitration solution is to use a priority scheme that gives priority to one of the ports. A flow chart illustrating the most common system, including the priority scheme solution, is shown in FIG. 1. The process starts, step 10, by determining if two ports are attempting to access the same cell at step 12. When the two ports are not attempting to access the same cell, the process waits for the beginning of the next cycle at step 14, and then repeats. When the two ports are attempting to access the same cell, the arbitration condition is latched favoring the priority channel at step 16. Next, the predecoder lines of the interfering port are inactivated for at least the duration of the overlapping addresses at step 18. This solution results in significantly limiting the performance of the non-priority or lower priority ports. Another problem found in the prior art is that the arbitration system locks out ports when there are multiple reads and no write operations. Yet another problem with some of the prior art solutions is that they block the other port(s') array access for a complete arbitration winning port's clock cycle. Since the clocks are generally asynchronous, the arbitration winning port's clock may have a significantly longer clock cycle than the other port(s) attempting to access the same memory cell. As a result, the losing port(s) may be blocked for multiple clock cycles, significantly reducing its/their performance.
Thus, there exists a need for a multi-port arbitration scheme that does not have priority channels, allows multiple simultaneous reads and does not block a port for any longer than is necessary.